Serob Avetisyan

Synopsys Armenia CJSC

• 4+ years of relevant experience in Layout design and verifications of Analog and Mixed-Signal structures( SRAM embedded memories ) in CMOS and FinFET technologies.

• Experience in all aspects of layout design, starting with the concept, through all phases of physical layout design implementations, strategies, and verifications ( LVS, DRC, ERC, PERC, DFM, Antenna Checks, etc.)

• Solid experience in techniques of custom layout floorplanning, hierarchical layout planning, and routing (device matching, isolation/shielding, ESD and Latch-up protection, avoidance of EM/IR)

• Sound knowledge of memory compilers, multiple abutment methodology

• Experience in design of high-performance and high-speed circuits (GHz)

• Strong leadership, troubleshooting, and communication skills

• Ability to learn new methodologies/techniques/flows

and technologies/processes very quickly

• Major Projects:

FOUNDRIES: TSMC, SAMSUNG, GF, INTEL

TECH NODES: 3nm, 5nm, 7nm, 4nm, 6nm